LSIs such as microprocessors are used by being mounted on circuit boards. It is rare that only an LSI is mounted on a circuit board. Usually, a decoupling capacitor is also mounted on the circuit board. The decoupling capacitor plays roles of reducing fluctuations in supply voltage line in a case of sudden fluctuations in the load impedance of the LSI or the like, and of reducing switching noise to stabilize the operation of the LSI in a high-frequency region of GHz. The performance of the decoupling capacitor needs to be improved in order to further enhance the speed of a semiconductor device such as an LSI and to further reduce the power consumption thereof. It should be noted that decoupling capacitors are also referred to as decoupling condensers or bypass condensers in some documents.
Between the decoupling capacitor and the LSI, wiring for electrically connecting them with each other is needed. If the wiring is too long, the inductances of the wiring makes it difficult for the decoupling capacitor to absorb the fluctuations in the supply voltage line and high-frequency ripples, and thereby, to sufficiently carry out the functions.
In view of this point, in Patent Document 1, a thin film capacitor is formed by stacking a dielectric layer and an electrode on a ceramic circuit board, thereby reducing the length of wiring between a capacitor and an LSI.
Moreover, Patent Documents 2 to 4 proposes an interposer type of capacitive element configured by stacking a lower electrode, a capacitor dielectric layer, and an upper electrode on a supporting substrate, and a structure in which the interposer type of capacitive element is interposed between a circuit board and an LSI.
FIGS. 1(a) and 1(b) are cross-sectional views of an LSI mounted on a circuit board using such an interposer type of capacitive element.
As shown in FIG. 1(a), in this conventional example, terminals 102 of a mother board 101 and terminals 104 of a mounting board 105 are electrically connected to each other by first solder bumps 103. In the mounting board 105, a depressed portion 105a is provided. In the depressed portion 105a, an interposer type of capacitive element 107 is accommodated. The capacitive element 107 and the mounting board 105 are electrically connected to each other by second solder bumps 106. In addition, third solder bumps 108 are provided on the upper surfaces respectively of the capacitive element 107 and the mounting board 105. Thus, a semiconductor element 109 such as an LSI is electrically connected to the capacitive element 107 and the mounting board 105 by the third solder bumps 108.
In the above-described structure, the capacitive element 107 is placed directly under the semiconductor element 109. Accordingly, the length of wiring between the semiconductor element 109 and the capacitive element 107 can be reduced. Moreover, the semiconductor element 109 is accommodated in the depressed portion 105a, thereby reducing the height of a package.
It should be noted that there is also a structure in which the depressed portion 105a is omitted as shown in FIG. 1(b), in the case where there is no need to reduce the height of the package as described above.
Hereinafter, a method of manufacturing a capacitive element used in the aforementioned structure of FIG. 1(a) will be described with reference to FIGS. 2(a) to 2(d). FIGS. 2(a) to 2(d) are cross-sectional views of a capacitive element of a conventional example in the process of being manufactured.
First, as shown in FIG. 2(a), an insulating layer 111 such as a silicon dioxide layer is formed on a silicon substrate 110. Then, a lower electrode 112, a capacitor dielectric layer 113, and an upper electrode 113 are formed thereon in this order.
A composite oxide dielectric material having a high relative dielectric constant is used for the capacitor dielectric layer 113 among these layers in order to obtain a large capacitor capacitance. As a material composing the lower electrode 112, platinum (Pt) or iridium (Ir) is used because they are materials which improve the crystalline orientation of the dielectric material and which can withstand a high-temperature environment during depositing the capacitor dielectric layer 113.
The lower electrode 112, the capacitor dielectric layer 113, and the upper electrode 114 described above constitute a capacitor Q.
Subsequently, as shown in FIG. 2(b), the upper electrode 112 and the capacitor dielectric layer 113 are patterned by the photolithography method, whereby a hole 115 having a depth which reaches the lower electrode 112 is formed in these layers.
Then, as shown in FIG. 2(c), photosensitive polyimide is applied to the entire surface by spin-coating and baked to be formed into an insulating protective layer 116. After that, this insulating protective layer 116 is exposed and developed, thus forming a lower electrode opening 116a in the hole 115 and forming an upper electrode opening 116b through which the upper electrode 114 is exposed.
Next, as shown in FIG. 2(d), by employing electro-plating and the like, a metal layer is formed in each of the openings 116a and 116b to be formed respectively into a lower electrode drawing pad 117 and an upper electrode drawing pad 118.
Thus, the basic structure of the capacitive element of the conventional example is completed.
When the polyimide constituting the insulating protective layer 116 is baked, water is released by a dehydration polycondensation reaction of acid anhydride and diamine constituting the polyimide. One example of the chemical formula thereof is shown in FIG. 3. In this example, in polyimide marketed in a varnish form, polyamic acid is produced from acid anhydride and diamine. By baking this polyamic acid, H2O is released due to a dehydration polycondensation reaction.
However, electrical characteristics of the capacitor dielectric layer 113 degrade due to a reducing atmosphere generated by water and the like. This may induce a short between the electrode layers 112 and 114. Such a problem is observed not only when the polyimide is baked, but also when water of an external environment is absorbed by the capacitor dielectric layer 113 and when the capacitor dielectric layer 113 is exposed to a reflow atmosphere for the solder bumps 106 and 108 (see FIG. 1(a)), which is a reducing atmosphere.
In particular, in the case where the lower electrode 112 is made of Pt, Pt produces radical hydrogen by catalysis with water, and the hydrogen easily passes through the Pt layer to reach the capacitor dielectric layer 113. Accordingly, a countermeasure to prevent degradation of the capacitor dielectric layer 113 is needed. In addition, this radical hydrogen causes oxygen deficiency in the capacitor dielectric layer at the interface with the lower electrode 112. This may also increase the leakage current of the capacitive element.
In view of this point, in a ferroelectric random access memory (FeRAM) in which a capacitor dielectric layer is made of a ferroelectric material, as described in Patent Document 5, a protective film made of nitride of any of silicon, titanium, and aluminum is formed to protect the capacitor dielectric layer.
In addition, in Patent Document 6, a hydrogen barrier layer is made of a nitride or an oxide any of titanium and iridium, and the hydrogen barrier layer prevents hydrogen from entering a capacitor dielectric layer.
Moreover, in Patent Document 7, it is also proposed to make a protective layer of metal organic compound (silicon alkoxides) which is hardened by reaction with water.
Furthermore, in Patent Document 8, it is proposed to make a protective layer of material, such as La5Ni, having the property of storing hydrogen.
Patent Document 1: Japanese Patent Application Publication No. Hei 04-211191
Patent Document 2: Japanese Patent Application Publication No. 2001-68583
Patent Document 3: Japanese Patent Application Publication No. 2001-35990
Patent Document 4: Japanese Patent Application Publication No. Hei 07-176453
Patent Document 5: Japanese Patent Application Publication No. Hei 07-111318
Patent Document 6: Japanese Patent Application Publication No. 2003-282827
Patent Document 7: Japanese Patent Application Publication No. Hei 07-273297
Patent Document 8: Japanese Patent Application Publication No. 2003-282830